Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same

ABSTRACT

A structure of trench VDMOS transistor comprises an n− epi-layer/ n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si layer. A plurality of MOS structure formed on the mesas. Doubled diffused source regions are formed asides the MOS structure. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer patterned as two is formed on inter-metal dielectric layer. The one is for source regions and the first poly-Si layer connection by source contact plugs and the other for the gate connection by gate contact plugs. In the other embodiment, the trenches are filled with a stack layer of a first oxide layer/a first poly-Si layer. The MOS gates with their second poly-Si layer in a form of rows are formed on the first oxide layer and the mesas. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer is formed on the inter-metal dielectric layer and through the source contact plugs connecting the source regions and the first poly-Si layer. The drain electrode is formed on the rear surface of the n+ substrate for both embodiments.

RELATED APPLICATION

This application is a divisional application of prior application Ser.No. 14/311,521, which was filed on Jun. 23, 2014 of which is pending andincorporated herein by reference.

FIELD OF THE INVENTION

The present invention pertains to a semiconductor device, inparticularly, to a structure of a trench-vertical doubled diffused MOStransistors and a method of making the same.

DESCRIPTION OF THE PRIOR ART

Among those of transistors with capability of withstand high reversebias voltage, the double-diffused metal oxide semiconductor transistorDMOS may be one of the most preferred. In the DMOS devices, the verticaldouble diffused metal oxide semiconductor (VDMOS) transistor attractsfurther attention than the lateral double-diffused metal oxidesemiconductor (LDMOS). The LDMOS structure is a planar device whereasthe VDMS is a trench structure and the VDMS is thus with advantages oflow cost and low open resistance (low on-resistance; RON). Parts ofreasons for that may be due to the latter component has a higherintegrated density and uses a whole rear surface side of thesemiconductor substrate as its drain electrode. The trench MOS is one ofVDMOS and with a higher integrated density than the average of VDMOS.

FIG 1a illustrates a conventional trench MOS disclosed in U.S. Pat. No.8,304,825. An n− epi-layer 15 on an n+ semiconductor substrate 10 hastrenches formed therein. A trench oxide layer 12 is then formed on thesidewall and the bottom of the trenches. A conductive poly-Si layer 13served as a gate region G is then filled in the trenches. The p− bodies14 having n+ implanted region 11 formed therein are served as sourceregions 11. The inter-metal dielectric layer 17 having contact holes isformed on the resulted surfaces. An interconnecting metal layer 19 isformed on the inter-metal dielectric layer 17 and filled the contactholes to form contact plugs. The interconnecting metal layer 19 throughsource contact plugs 18 connected to the source regions 11. Anotherinterconnecting metal layer (not shown) is connected to the trench gate.The drain electrode 10 is a metal layer formed on the rear surface ofthe n+ semiconductor substrate.

FIG. 1b shows a top view illustrating an interconnecting metal layer 19connected to the source regions 11 by source contact pads Scp. Theinterconnecting metal layer for gates Gp are connected to the poly-Silayer 13 through the gate contact pad Gcp.

SUMMARY OF THE INVENTION

An object of the present invention is to disclose a trench verticaldoubled diffused MOS transistor (VDMOS transistor).

According to a first preferred embodiment, the VDMOS transistorcomprises an n− epi-layer on a n+ semiconductor substrate having aplurality of trenches in parallel formed therein and the trenches arespaced each other by a mesa; each of the trenches has a trench oxidelayer formed on a bottom and sidewalls and a first conductive poly-Silayer filled in the trench; a plurality of planar gates having a secondpoly-Si layer on a planar gate oxide layer are formed on the mesas; aplurality of source regions are formed in the n− epi-layer at the mesasasides the planar gates; each of the source regions is a region havingdoubled diffused impurities formed therein; an inter-metal dielectriclayer having source contact holes and gate contact holes formed therein,is formed on the source regions, the first poly-Si layer, and the planargates; a first interconnecting metal layer is formed on the inter-metaldielectric layer and connected to the source regions through the sourcecontact plugs; a second interconnecting metal layer is formed on theinter-metal dielectric layer and connected to the planar gate throughthe gate contact plugs; and a rear metal layer served as a drainelectrode is formed on a rear surface of the n+ semiconductor substrate;each of the source regions includes a p body, a shallower n+ regionextended to the mesa surface formed in the p body, and a p+ regionformed in the p body right at a bottom of the source contact plug.

According to a second preferred embodiment, the VDMOS transistorcomprises a n− epi-layer on a n+ semiconductor substrate having aplurality of trenches formed in parallel therein and the trenches spacedeach other by a mesa; each of the trenches has a trench oxide layerformed on a bottom and sidewall and a stack of first oxide layer/ afirst conductive poly-Si layer filled in the trench; a planar gate oxidelayer is formed on the mesas and a plurality of rows of a second poly-Silayer extended to the ends of the substrate, are formed on the planargate oxide layer and the first oxide layer; a plurality of sourceregions are formed in the n− epi-layer asides the planar gates; each ofthe source regions is a region having doubled diffused impurities formedtherein; an inter-metal dielectric layer having source contact holes, isformed on the source regions, the first oxide layer, and the planargates; a interconnection metal layer is formed on the inter-metaldielectric layer and is connected to the source regions through thesource contact plugs; a interconnection metal layer is formed on theinter-metal dielectric layer and connected to the planar gate throughthe source contact plugs; and a rear metal layer served as a drainelectrode is formed on a rear surface of said n+ semiconductorsubstrate. Each of the source regions includes a p body, a shallower n+region extended to the mesa surface formed in the p body, and a p+region formed in the p body at a bottom of the source contact plugs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a is a cross-sectional view illustrating a trench MOS transistorin accordance with a prior art;

FIG. 1b is a top view illustrating the trench MOS transistor inaccordance with the prior art;

FIG. 2a is a top view illustrating a VDMOS transistor (interconnectingmetal layers not shown) in accordance with the first preferredembodiment of the present invention;

FIG. 2b is a top view illustrating a VDMOS transistor (aninterconnecting metal layer not shown) in accordance with the secondpreferred embodiment of the present invention;

FIG. 3 is a cross-sectional view illustrating a plurality of trenchesformed in the n− epitaxial layer and a trench oxide layer successivelyformed thereon in accordance with the first preferred embodiment of thepresent invention;

FIG. 4 is a cross-sectional view illustrating a first conductive poly-Silayer refilled in the trenches until overfilled and then an etch backperformed to remove the first poly-Si layer and the trench oxide layerover the mesas in accordance with the first preferred embodiment of thepresent invention;

FIG. 5A, FIG. 5B and FIG. 5C are cross-sectional views respectively,along the A-A′ line, the B-B′ line and the C-C′ line shown in FIG. 2aillustrating a photoresist pattern formed on a second conductive poly-Silayer to define positions of gates and source regions in accordance withthe first preferred embodiment of the present invention;

FIG. 6A, FIG. 6B and FIG. 6C are cross-sectional views respectively,along the A-A′ line, the B-B′ line and the C-C′ line shown in FIG. 2aillustrating a patterned second conductive poly-Si layer as planar gatesand source regions having doubled diffused impurities formed asides theplanar gates in accordance with the first preferred embodiment of thepresent invention;

FIG. 7A, FIG. 7B and FIG. 7C are the cross-sectional views respectively,along the A-A′ line, the B-B′ line and the C-C′ line shown in FIG. 2aillustrating an inter-metal dielectric layer formed on the resultedsurfaces and a photoresist pattern formed and patterned to form sourcecontact holes and gate contact holes in accordance with the firstpreferred embodiment of the present invention;

FIG. 8A, FIG. 8B and FIG. 8C are the cross-sectional views respectively,along the A-A′ line, the B-B′ line and the C-C′ line shown in FIG. 2aillustrating the final structure of a VDMOS transistor in accordancewith the first preferred embodiment of the present invention;

FIG. 9 is a cross-sectional view illustrating a first poly-Si layerfilled in the trenches and then an etch back performed to form recessesin the trenches in accordance with the second preferred embodiment ofthe present invention;

FIG. 10 is a cross-sectional view illustrating a first oxide layeroverfilled the trenches in accordance with the second preferredembodiment of the present invention;

FIG. 11 is a cross-sectional view illustrating an etch back performedusing the n− epi-layer as an etch stop layer in accordance with thesecond preferred embodiment of the present invention;

FIG. 12A, FIG. 12B and FIG. 12C are the cross-sectional viewsrespectively, along the A-A′ line, the B-B′ line and the C-C′ line shownin FIG. 2b illustrating a photoresist pattern formed on the secondpoly-Si layer to define a plurality of rows of the second poly-Si layerin accordance with the second preferred embodiment of the presentinvention;

FIG. 13A, FIG. 13B and FIG. 13C are the cross-sectional viewsrespectively, along the A-A′ line, the B-B′ line and the C-C′ line shownin FIG. 2b illustrating a patterned second poly-Si layer and doubleddiffused source regions formed asides the gates in accordance with thesecond preferred embodiment of the present invention;

FIG. 14A, FIG. 14B and FIG. 14C are the cross-sectional viewsrespectively, along the A-A′ line, the B-B′ line and the C-C′ line shownin FIG. 2b illustrating an inter-metal dielectric layer formed on theresulted surfaces and a photoresist pattern formed and patterned to formsource contact holes in accordance with the second preferred embodimentof the present invention;

FIG. 15A, FIG. 15B and FIG. 15C are the cross-sectional viewsrespectively, along the A-A′ line, the B-B′ line and the C-C′ line shownin FIG. 2b illustrating the final structure of a VDMOS transistor inaccordance with the second preferred embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention discloses a trench-vertical doubled diffused MOStransistor, hereinafter called a VDMOS transistor. Please refer to a topview shown in FIG. 2a and its corresponding cross-sectional views shownin FIG. 8A to 8C according to a first preferred embodiment of thepresent invention and a top view shown in FIG. 2b and its correspondingcross-sectional views shown in FIG. 15A to 15C according to a secondpreferred embodiment of the present invention. Hereinafter, theuppercase A, B, C in FIG. # A, FIG. # B, FIG. #C represent,respectively, along the cutting lines AA′, BB′ and CC′ of the top viewsFIG. 2a or FIG. 2 b. The label “+” and “−” following n or p represent,respectively, heavily doped (implanted) and lightly doped (implanted).To facilitate illustrating the detailed structure, the interconnectingmetal layers 191 s, 191 g do not shown in the top plan views. As to thedetailed connection relationship between elements in the semiconductordevice, please refer to the cross-sectional views shown in FIG. 8A, FIG.8B, and FIG. 8C.

In accordance with a first preferred embodiment of the presentinvention, a trench VDMOS transistor is illustrated in the plan-viewFIG. 2a and its cross-sectional views, FIG. 8A, FIG. 8B and FIG. 8C. Thefigures show an n− epi-layer 105 on a n+ semiconductor substrate 100having a plurality of trenches 115 in parallel and spaced each otherwith a mesa 118 formed therein. A trench oxide layer 120 is conformallyformed on bottoms and sidewalls of the trenches 115. A first poly-Silayer 130 having conductive impurities in-situ doped is formed on thetrench oxide layer 120 and filled in the trenches 115. A planar gateoxide layer 127 is formed on the mesas 118 and on the first poly-Silayer 130. A second poly-Si layer 140 having conductive impuritiesin-situ doped is formed on the planar gate oxide layer 127. The MOSgates are formed on the mesas 118 by patterning the second poly-Si layer140 and the planar gate oxide layer 127 thereunder. Aside the MOS gatesare source regions having n+ implanted regions 155 extended to thesurface of the n epi-layer 105 formed in the p body. Each source regionfurther comprises a p+ region 165 formed under n+ implanted region 155formed in the p body 135. The source contact pads SP are formed toconnect n+ implanted regions 155 and p+ regions 165. The source contactpads SP are also connected the first poly-Si layer 130 in the trenches.The gate contact pads GP are formed on the second poly-Si layer 140.

In accordance with a second preferred embodiment of the presentinvention, a trench VDMOS transistor is illustrated in the plan-viewFIG. 2b and its cross-sectional views, FIG. 15A, FIG. 15B and FIG. 15C.The figures show an n− epi-layer 105 on a n+ semiconductor substrate 100having a plurality of trenches 115 in parallel and spaced each otherwith a mesa 118 formed therein. A trench oxide layer 120 is conformallyformed on bottoms and sidewalls of the trenches 115. A stack layer of afirst oxide layer 13/a first conductive poly-Si layer 130 filled in thetrenches 115. A planar gate oxide layer 127 is formed on the mesas 118.A plurality of rows of a second conductive poly-Si layer 140 extended toends of the n+ substrate 100 are formed on the planar gate oxide layer127 and the oxide layer 137 along a transversal direction of thetrenches.

Asides the rows of the rows of the second poly-Si layer 140 are sourceregions formed in the n− epi-layer 105. Each of the source regions has ashallow n+ implanted region 155 extended to the mesa 118 formed into thep body 135. An inter-metal dielectric layer 185 formed on the resultedexposed surfaces. The inter-metal dielectric layer 185 has a pluralityof source contact holes 187 s formed therein. An interconnecting metallayer 191 s is formed on the inter-metal dielectric layer 185 and filledin the source contact holes as source contact plugs 188 s connecting thesource region and the first poly-Si layer 130 through the first oxidelayer 135. Under the source contact plugs 188 s are p+ implanted regions165 as source contact pads SP formed in the p body 135. A rear metallayer 195 served as a drain electrode formed on the rear n+ substrate100.

The detailed processes for forming the structure of VDMOS transistor areas follows.

Please refer to FIG 3. The cross-sectional view depicts an n− epi-layer105 on an n+ semiconductor substrate 100 having a plurality of trenches115 in parallel formed therein and spaced each other with a mesa 118.The trenches 115 may be formed by a dry etch using a photoresist patternlayer or a hard mask layer with a patterned nitride layer/pad oxide asan etching mask (not shown).

Subsequently, a thermal oxidation process is carried out to form atrench oxide layer 120 conformally formed on the sidewalls and bottomsof the trenches and the mesas 118. The processes can repair the damageduring etching.

Referring to FIG. 4 a first poly-Si layer 130 with in-situ dopedconductive impurities is deposited within the trenches 115 untiloverfilled. Thereafter, an etching back or a chemical mechanicalpolishing (CMP) technology is performed to remove the first poly-Silayer 130 over the mesas 118 and the trench oxide layer on the mesas 118using the surface of the n− epi-layer 105 as an etching stop layer.

Still referring to FIG. 4, a thermal oxidation is carried out to form aplanar gate oxide layer 127 on the first poly-Si layer 130 and the mesa118. The planar gate oxide layer 127 is a thinning oxide layer than thetrench oxide layer 120. Subsequently, a second poly-Si layer 140 isdeposited on the planar gate oxide layer 127. A photoresist pattern 142is formed on the second poly-Si layer 140 to define the positions of theplanar MOS gate structure. FIG. 5A and FIG. 5B are, respectively, twocross-sectional views along a cutting line AA′ and a cutting line BB′ ofFIG. 2a which are along two transversal directions of the trenches 115.FIG. 5C is a cross-sectional view along a cutting line CC′ of FIG. 2a ,which is along a longitudinal direction of the trench 115. Along the BB′cutting line, the second poly-Si layer 140 is exposed without aphotoresist mask 142.

Please refer to FIG. 6A, FIG. 6B and FIG. 6C. An anisotropic etch isperformed to pattern the second poly-Si layer 140 using the photoresistpattern 142 as an etching mask. The second poly-Si layer 140 is removedalong the cutting line BB′. The discrete MOS gates are formed on themesas 118. After a removal of photoresist pattern layer 142, a first ionimplantation is performed to form p bodies 135 in the n− epi-layer 105by implanting p type impurities such as B⁺ or BF₂ ⁺. The dosages and theenergy for the first ion implantation are 1E12-1E14/cm² and 10 keV-1000keV, respectively. A second ion implantation by n type impurities suchas P⁺ and As⁺ ions with a lower energy are performed to form a shallowern+ regions 155 in the p bodies 135. The doses for second ionimplantation are between about 1E13-9E15/cm², which are higher than thatof the first ion implantation by 1-2 order(s) of magnitude.

Referring to cross-sectional views FIG. 7A, FIG. 7B and FIG. 7C, aninter-metal dielectric layer 185 is deposited on the resulted surfaces.Subsequently, a photoresist pattern 186 is formed on the inter-metaldielectric layer 185 to define source contact holes 187 s and gatecontact holes 187 g. Please refer to FIG. 2a , too. Along the cuttingline AA′ of FIG. 2a , the inter-metal dielectric layer 185 is formedwith gate contact holes 187 g to connect the second poly-Si layer 140.Along the cutting line BB′ of FIG. 2a , the inter-metal dielectric layer185 is formed with source contact holes 187 s to connect the firstpoly-Si layer 130 and the source regions under the mesas 118.

Thereafter, an anisotropic dry etch is performed to pattern theinter-metal dielectric layer 185, the planar gate oxide layer 127, usingthe n− epi-layer 105 as an etching stop layer. Then a timing controletch is successively performed to remove the exposed n+ implantedregions 155. After the photoresist layer 186 is removed, a third ionimplantation through the contact holes is carried out to form p+ regions165 in the p bodies 135. After the ion implantations, an anneal processat a temperature between about 800-1000° C. to activate the impuritiesare carried out.

Subsequently, an interconnecting metal layer is deposited on theinter-metal dielectric layer 185 and filled in the contact holes 187 sand 187 g by sputtering. The interconnection metal layer is thenpatterned to two separate groups 191 s and 191 g. Group 191 s connectsthe source region and the first poly-Si layer 130 through the sourcecontact plugs 188 s, as shown in FIG. 8B. Group 191 g connects thesecond poly-Si layer 140 through the gate contact plugs 188 g, as shownin FIG. 8B. The FIG. 8C shows 191 s separated from the second 191 g.

The interconnecting metal layer 191 s, 191 g may be a stack layer ofTi/TiN, TiNi/Ag or TiW/Al or a single metal layer formed of aluminum.The drain electrode of the VDMOS transistor is a rear metal layer 195formed on the rear side of the n+ semiconductor 100.

Refer to FIG. 8C, interconnection metal group 191 s consists of separatestripes needed to be connected together and connected to source pad,also interconnection metal group 191 g consists of separate stripesneeded to be connected together and connected to gate pad. The two padscannot be connected with each other, so one more layer of interconnectmetal, IMD and via are needed. The method to form the pads is obviousfrom this point thus not described.

According to a second preferred embodiment, the illustrating diagram isstarted from the FIG. 9, which is followed from the FIG. 3. A firstconductive poly-Si layer 130 is deposited on the trench oxide layer 120until the poly-Si layer 130 overfilled the trenches 115. An etching backprocess is performed to remove the overfilled portion and further recessthe first poly-Si layer 130 significantly. A first oxide layer 137 isthen deposited to fill the recesses in the trenches 115 untiloverfilled. A CMP or a second etching back process is carried out toremove the first oxide layer 137 and the exposed planar gate oxide layer127 using the n− epi-layer 105 as an etching stop layer. The results areshown in the FIG. 11.

Thereafter, a thermal process is performed to form the planar oxidelayer 127 again, and a second poly-Si layer 140 with in-situ dopedconductive impurities deposited on the planar gate oxide layer 127 isfollowed. A photoresist pattern 142 is formed on the second poly-Silayer 140 to define a plurality of rows of the second poly-Si layer 140as gates, as shown in cross-sectional views FIG. 12A, FIG. 12B and FIG.12C,

Along the cutting line AA′ of FIG. 2b , the photoresist pattern 142 ismasked on the second poly-Si layer 140. The rows of the second poly-Silayer 140 s are along a transversal direction of the trenches 115.Please refer to FIG. 13, FIG. 13B and FIG. 13C, an anisotropic etch isperformed to pattern the second poly-Si layer 140 using the photoresistpattern 142 as an etching mask. The second poly-Si layer 140 is removedalong the cutting line BB′ of FIG. 2b , After a removal of photoresistpattern layer 142, a first ion implantation is performed to form pbodies 135 in the n− epi-layer 105 by implanting p type impurities suchas B⁺ or BF₂ ⁺. The dosages and the energy for the first ionimplantation are 1E12-1E14/cm² and 10 keV-1000 keV, respectively. Asecond ion implantation by n type impurities such as P⁺ and A⁺ ions witha lower energy are performed to form a shallower n+ regions 155 in the pbodies 135. The doses for second ion implantation are between about1E13-9E15/cm², which are higher than that of the first ion implantationby 1-2 order(s) of magnitude.

Referring to cross-sectional views of FIG. 14A, FIG. 14B and FIG. 14C,an inter-metal dielectric layer 185 is deposited on the resultedsurfaces. Subsequently, a photoresist pattern 186 is formed on theinter-metal dielectric layer 185 to define the positions of sourcecontact holes 187 s. An anisotropic dry etch is performed to form sourcecontact holes 187 s by patterning the inter-metal dielectric layer 185,the planar gate oxide layer 127 and the first oxide layer 137, using then− epi-layer 105 as an etching stop layer. Then a timing control etch issuccessively performed to remove the exposed n+ implanted regions 155.After the photoresist layer 186 is removed, a third ion implantation iscarried out through the source contact holes 187 s to form p+ regions165 in the p bodies 135. After the ion implantations, an anneal processat a temperature between about 800-1000° C. to activate the impuritiesare carried out.

Subsequently, an interconnecting metal layer 191 s is deposited on theinter-metal dielectric layer 185 and filled in the source contact holes187 s by sputtering. The results are shown in FIGS. 15A, 15B, and 15C.The interconnecting metal layer connected to the source regions and thefirst poly-Si layer 130 through source contact plugs 188 s, as shown inFIG. 15A, FIG. 15B, and FIG. 15C. The interconnecting metal layer 191 s,191 g may be a stack layer of Ti/TiN, TiNi/Ag or TiW/Al or a singlemetal layer formed of aluminum. The rows of the second poly-Si layer 140served as gates, which is extended to the ends of the substrate 100. Thedrain electrode of the VDMOS is a rear metal layer 195 formed on therear side of the n+ semiconductor 100.

In the second preferred embodiment, the gate contact plugs are formed onthe ends of the second poly-Si layer 140 only.

The benefits of the present invention are:

-   (1). The VDMOS transistor according to the present invention has a    better capability of reverse break down voltage performance than the    prior art, shown in FIG. 1 while the resistivity of the n-epi layer    is the same as that of prior art.-   (2). The VDMOS transistor according to the present invention    includes a planar MOS gate whose planar gate oxide layer 127 is much    thinner than the trench gate oxide layer 120 so that the VDMOS    transistor has a lower threshold forward voltage than the VDMOS    transistor in accordance with the prior art, shown in FIG. 1.

As is understood by a person skilled in the art, the foregoing preferredembodiments of the present invention are illustrated of the presentinvention rather than limiting of the present invention. It is intendedto cover various modifications and similar arrangements included withinthe spirit and scope of the appended claims, the scope of which shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar structures. For instance, the aforementionedexemplary embodiments are illustrated by n type VDMOS transistor formedon the n type substrate; the processes may be applied to form p-typeVDMOS transistor formed on p type substrate.

What is claimed is:
 1. A method of forming a trench vertical doubleddiffused transistor (VDMOS transistor), said method comprising the stepsof: providing an impurity-lightly doped epi-layer of a first conductivetype having a plurality of mesas and trenches, said trenches spaced eachother by one of said mesas formed in parallel therein on animpurity-heavily doped semiconductor substrate of said first conductivetype; forming a trench oxide layer on a bottom and sidewalls of each ofsaid trenches and said mesas; forming a first conductive poly-Si layerto fill over said trenches; recessing said first conductive poly-Silayer to form recesses in said trenches; deposited a first oxide layerover said recesses and said mesas; etching back said first oxide layerusing said epi-layer as an etching stop; forming a gate oxide layer onsaid mesas; forming a second conductive poly-Si layer on said firstoxide layer and said gate oxide layer; forming a first photoresistpattern on said second conductive poly-Si layer, said first photoresistpattern having a plurality of rows of openings in parallel, each of saidrows of openings along a transversal direction of said trenches;patterning said second conductive poly-Si layer to form a plurality ofrows of second poly-gates and expose said gate oxide layer and saidfirst oxide layer, using said first photoresist pattern as an etchingmask; performing a first ion implantation through said gate oxide layerwith high implanting energy and impurities of a second conductive typeto form bodies in said mesas; performing a second ion implantationthrough said gate oxide layer with low implanting energy and impuritiesheavily of said first conductive type to form implanting regions oversaid bodies in said mesas; stripping said first photoresist pattern;forming an inter-level dielectric layer on said second poly-gates, andsaid mesas and said first oxide layer; forming a second photoresistpattern on said inter-level oxide layer having openings to exposepredetermined regions of source contact holes; anisotropic etching saidinter-level dielectric layer, said first oxide layer, and said epi-layerat said mesas to form source contact holes; performing a third ionimplantation to implant impurities heavily of said second conductivetype into bottoms of said source contact holes; removing said secondphotoresist pattern; forming an upper metal layer on said inter-leveldielectric layer and fill said source contact holes to form sourcecontacts. milling a rear surface of said semiconductor substrate tillpredetermined thickness; forming a bottom metal layer on said rearsurface of said semiconductor substrate as a drain electrode.
 2. Themethod of forming a trench vertical doubled diffused transistor (VDMOStransistor) according to claim 1 wherein said source contacts contactsaid first poly-Si conductive layer, said implanting regions of saidfirst conductive type and said bodies of said second conductive type. 3.The method of forming a trench vertical doubled diffused transistor(VDMOS transistor) according to claim 1 wherein said first oxide in saidtrenches having a thickness significantly than that of said gate oxidelayer so as to insulate said first conductive poly-Si from beingaffected by a voltage exerting on said second poly-gates.